1. general description the 74hc27; 74hct27 is a triple 3-input nor gate. inputs include clamp diodes. this enables the use of current limiting resistors to interface inputs to voltages in excess of v cc . 2. features and benefits ? complies with jedec standard no. 7a ? input levels: ? for 74hc27: cmos level ? for 74hct27: ttl level ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? multiple package options ? specified from ? 40 ? cto+85 ? c and from ? 40 ? cto+125 ? c 3. ordering information 74hc27; 74hct27 triple 3-input nor gate rev. 4 ? 5 june 2013 product data sheet table 1. ordering information type number package temperature range name description version 74hc27n ? 40 ? c to +125 ? c dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 74hct27n 74hc27d ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct27d 74hc27db ? 40 ? c to +125 ? c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74hct27db 74hc27pw ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74hct27pw 74hc27bq ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74HCT27BQ
74hc_hct27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 4 ? 5 june 2013 2 of 17 nxp semiconductors 74hc27; 74hct27 triple 3-input nor gate 4. functional diagram 5. pinning information 5.1 pinning fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) mna936 1a 1b 1y 2 1 12 1c 13 2a 2b 2y 4 3 6 2c 5 3a 3b 3y 10 9 8 3c 11 mna935 12 1 1 1 2 1 6 4 3 8 10 9 13 5 11 mna937 a b c y (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration dip14, so14, (t )ssop14 fig 5. pin configuration dhvqfn14 74hc27 74hct27 1a v cc 1b 1c 2a 1y 2b 3c 2c 3b 2y 3a gnd 3y 001aag759 1 2 3 4 5 6 7 8 10 9 12 11 14 13 d d d + & |